Published Paper Details:

Network security is concerned with the protection of network resources against alteration, destruction and unauthorized use, cryptography and encryption are most critical components of network security. There are many algorithms to protect the sensitive data that is sent on the communication media. Implementing this cryptographic algorithm on software platform will overburden the server. To offload the server from cryptographic operations a lot of efficient hardware implementation of AES are available in open literature on ASIC and FPGA platforms. In modern technology, FPGAs are equipped with some special embedded features to achieve high performance design and density. These embedded features to be used efficiently to enhance the performance in terms of both area and speed. Here we propose hardware efficient Hybrid Wireless Crypto Processor (HWCP) which combines two block ciphers such as enhanced advanced encryption standard (AES) and side-channel resistant authenticated encryption with masking (SCREAM). This proposed HWCP system maximizes the security via increasing the complexity of cracking keys.