Published Paper Details:

Power dissipation is a key factor for mobile devices and other low power applications. Complementary metal oxide semiconductor (CMOS) is the dominant integrated circuit (IC) technology responsible for a large part of this power dissipation. As the minimum feature size of CMOS devices enters into the sub 50 nanometer (nm) regime, power dissipation becomes much worse due to intrinsic physical limits. Many approaches have been studied at device and circuit level to reduce power dissipation of deeply scaled CMOS ICs. However, these approaches have unavoidable drawbacks which affect the performance as well as cost of device. Therefore, there is a strong need to find an emerging technology, which has nearly zero leakage current, but has high drive current, that also can utilize CMOS fabrication and design concepts, and can be integrated with CMOS technology without additional overhead. This paper focuses on the analysis, design, characteristics and applications of MOSFET replacement devices, with emphasis on the suspended gate FET (SGFET). Recently, the suspended-gate MOSFET (SG-MOSFET) was investigated as a possible candidate for ultra low power devices on the basis of numerical simulation and analytical modeling. Here, the comparison study is made between the SGFET structure which has been reported earlier and the new structure in which the dimensions are scaled to analysis the characteristics of scaled SGFET for ultra low power devices.