Published Paper Details:

The adder is a digital circuit that can multiply two numbers. The half adder, sometimes known as the full adder, is a device that adds single-bit integers together. To increase the bit size of a number, we utilize parallel adders, which are made up of a series of complete adders, such as the carry save adder (CSA), carry select adder (CSLA), carry skip adder (CSKA), and so on. The speed of addition is limited by the time it takes for a carry to propagate through a digital adder. In a simple adder, the total for each bit position is calculated sequentially after the previous bit position has been summed and a carry has been transferred to the next place. The binary adder is used in almost all digital circuit designs, including digital signal processors (DSP) and microprocessor data path units. Power consumption, area, and speed are all important considerations in VLSI design. There are various methods for reducing power use and saving space. A carry skip adder (CSKA) is employed in this project, as well as a square root carry select adder (CSLA). The suggested design consumes less energy and occupies less space than the current one. Furthermore, as compared to earlier designs, the hardware complexity is minimized. This project uses the Xilinx-ISE 14.7 tool for simulation, logical verification, and further synthesizing, using VERILOG as the HDL language.