Published Paper Details:

The multiply-accumulate (MAC) architecture presented in this study makes use of Vedic mathematics to achieve excellent efficiency with minimal space requirements. While several MAC designs have implemented partial product reduction in multipliers to cut down on latency, this has introduced the additional challenge of dealing with overflow during the addition phase. This architecture, while efficient and advantageous to performance, is made in a sophisticated manner. To address this issue, we present a novel strategy that achieves state-of-the-art performance in terms of both space and delay. With the help of the ancient Indian mathematical treatise Urdhva-Tiryagbhyam sutra, we've developed a multiplier that saves the prior value in one register and uses the current value in the other, establishing a MAC architecture that saves valuable space by using only two input registers. The multiplier is an essential part of any high-performance MAC because it is used in digital signal processing systems and general processors. Finally, we will evaluate the efficiency of the proposed method versus the existing one.