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  Published Paper Details:

  Paper Title

LINEAR THRESHOLD TUNNELING TECHNOLOGY BASED LOGIC GATES, FULL ADDER AND A CONVERTER

  Authors

  ANUP KUMAR BISWAS

  Keywords

Key words: up-down Counter, Electron-tunneling, Coulomb-blockade, linear threshold gate

  Abstract


ABSTRACT In business, engineering, science and technology, electronic goods of Low cost, low power consumption, high operating speed, and high integration density are economically requisite in the present era. Single Electron tunneling based threshold gate is one approach with which we are able to implement all logic gates, combinational and sequential circuits. Threshold Logic Gates (TLGs) and Single Electron tunneling devices (SEDs) bear the capabilities of controlling the transport of an electron through a tunnel junction at a particular time. A single electron containing the charge is sufficient to store an information in a SED. Power that is required in the single electron tunneling circuits is really low in comparison with the (CMOS) circuits. The processing delay is very low and speed of the processing of TLG based devices will be close to electronic speed. The single-electron transistor (SET) and TLG are attracting scientists, technologists and researchers to design and implement for the consuming of ultra-low power and their small sizes. All tunneling events in a TLG-based circuit happens when only a single electron tunnels from one conductor to other through the tunnel junction when the bias voltage and multiple input signal voltages are applied. For implementing logic gates, Full adder and a converter, TLG would be a best candidate to fulfill the necessities needed for their implementations. So far as an Ultra-low noise is concerned, TLG based circuit can be considered to be a best selection for implementing the desired tunneling circuits. Different TLGs like 2-input AND, 2-input OR, 3-input AND/NAND, 3-input OR/NOR, XOR/XNOR, Full adder, and a converter of BCD-to-Excess-3 have been implemented by using linear threshold logic gates or devices. Truth table or simulated results of them are given in parallel in due places.

  IJCRT's Publication Details

  Unique Identification Number - IJCRT2106314

  Paper ID - 208640

  Page Number(s) - c571-c590

  Pubished in - Volume 9 | Issue 6 | June 2021

  DOI (Digital Object Identifier) -   

  Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882

  E-ISSN Number - 2320-2882

  Cite this article

  ANUP KUMAR BISWAS,   "LINEAR THRESHOLD TUNNELING TECHNOLOGY BASED LOGIC GATES, FULL ADDER AND A CONVERTER", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.9, Issue 6, pp.c571-c590, June 2021, Available at :http://www.ijcrt.org/papers/IJCRT2106314.pdf

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ISSN: 2320-2882
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Journal Starting Year (ESTD) : 2013
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ISSN and 7.97 Impact Factor Details


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ISSN
ISSN: 2320-2882
Impact Factor: 7.97 and ISSN APPROVED
Journal Starting Year (ESTD) : 2013
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