Published Paper Details:

In synchronous or clocked sequential networks, clocked flip-flops are used as memory elements, which change their individual states in synchronism with the periodic clock signal. Therefore, the change in status of flip-flops and change in state of the entire circuit occurs at the transition of the clock signal. The key to the proper operation of a flip-flop is to trigger it only during a signal transition. A clock pulse goes through two transitions from 0 to 1 and the return is from 1 to 0. The positive transition is defined as the positive-edge and the negative transition as the negative-edge. The single-edge triggered flip-flop (SETFF) fetches the data either on the rising or the falling edge of the clock cycle, but dual edge triggered sense amplifier flip-flop (DETSAFF) utilizes both the edge of the clock signal. The clock gating is another popular technique to reduce the dynamic power consumption when the system is idle. We give a wide knowledge of the DETSAFF and study has been made on several DETSAFF architectures by reviewing several papers.