Published Paper Details:

Multiplication is the basic arithmetic operation. In DSP (digital signal processing) a lot of arithmetic operations require the use of multiplications. The performance of 3D computer graphics, gaming, Embedded systems, DSP etc, are particularly depends on the performance of multiplication steps. Multipliers have more area, long latency and consume high amount of power. Critical factors in the design of multipliers are chip area and speed of multiplication and require less hardware. Scaling of technology node increases power-density more than expected. This paper is focused on Multi Precision (MP) reconfigurable multiplier combined with various precision methods, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and MP operands scheduling to give optimum level of performance for various operating conditions. Adapting to the run-time workload of the targeted application, razor flip-flops combine with a dithering voltage unit, because of this the multiplier is able to achieve the lowest power consumption. Use of single switch dithering voltage unit and razor flip-flops help to minimize the safety margins in voltage and overhead in DVS. The more amount of silicon area and power requirements are reduced because of reconfigurable structures. In this paper we design the multiplier in three ways and compare their performance. We can obtain the efficiency and also achieve silicon area reduction in the range of 11.1% by using AIMS 0.35 technology. Using ModelSim6.3 software we can design the multiplier structure and Xilinx synthesis Tool is used for power and area analysis.