Published Paper Details:

For designing high speed digital systems, it consider so many factors, among those the Number System, what it uses plays a crucial role. The selected number system must provide inherent properties such as Carry-free operations, Parallelism and Fault Tolerance. All these can be achieved with the use of Residue Number System (RNS). The RNS is an unconventional number system i.e., defined in terms of relatively Prime Moduli Set {m1, m2,.....,mn} that GCD (mi,mj) =1 for i?j. The RNS based system contains three major blocks, such as Forward Converter, RNS Processor and Reverse Converter. For Reverse conversion two algorithms are used i.e. Chinese Remainder Theorem (CRT) and Mixed Radix Conversion (MRC). The CRT is desirable; because of the data conversion can be parallelized, while MRC is a sequential process by its nature. While designing RNS, the selection of choice of moduli set plays a key role. The 3n-bit dynamic range RNS moduli set {2n-1, 2n, 2n+1} is the most famous RNS moduli set because of its simple and well formed balanced moduli. However, the arithmetic operations with respect to the modulus 2n+1 are complex and dynamic range is not sufficient for applications that require larger dynamic range. The 4n-bit dynamic range four moduli set minimize the dynamic range, and have long conversion delay and asymmetric moduli channel length. In this paper, a special five moduli set (2n-1, 2n, 2n+1, 2n+1-1, 2n-1-1) for even n is proposed. It has high dynamic range (m1*m2*m3*m4*m5), while keeping the moduli small enough and converter efficient. In this paper reverse converter design is done with the CRT and the results are compared with the MRC and also with the three and four moduli sets. The required language is Verilog HDL, and the required Software tool is Xilinx ISE Design Suite 14.7. The simulator is ISim (VHDL/Verilog) and the synthesis tool is XST (VHDL/Verilog).