Published Paper Details:

Carbon Nanotube plays a major role in electronic industry to produce large number of electronic devices. The main reason behind is the dimension of CNT in nanometer size. Carbon Nanotube filed-effect transistor (CNTFET) is one of the promising alternatives to the MOS transistors. The geometry-dependent on threshold voltage are one of the CNTFET characteristics, which are used to design parallel adder. This paper presents a low voltage and high performance 4-bit parallel adder which is used to reduce the power delay product (PDP).This technique is mainly implemented by using static energy recovery full adder based on CNTFET model where we can reduce the power consumption and delay. Full adder is designed using 10 transistors. Simulation results show significant improvement in terms of power, delay and power-delay product in comparison between FA and PA .Simulations were carried out using HSPICE based on CNTFET model with 0.7v and 0.9v VDD.