Published Paper Details:

AES is one of the standard algorithm and widely used to encrypt and decrypt the data. In this paper, image encryption and decryption algorithm is implemented by using AES 128-bit core. Here, image information is converted into a hexadecimal format using MATLAB code and this plain hexadecimal data are transmitted to the FPGA via UART for encryption. Thus, the same process is al so used for Decryption. The entire AES 128-bit core is simulated and synthesized for Spartan-3E-1600E FPGA using Xilinx ISE 14.3 and implementing on FPGA. By this design we calculate Throughput and observe Memory Allocation, Timing Report, Power Distribution and Device Utilization. To achieve high security to data, less power consumption and gives low complexity architecture. It’s applicable in Defense and Research Organizations for send secure data from third party and make it easy for other Software and Hardware applications.. Results prove area utilization is less when compared to other results.