Published Paper Details:

: The power consumption of Modern digital circuits has two components. The dynamic power is consumed only when the circuit performs a function and signals change. Leakage or static power is consumed all the time, i.e., even when the circuit is idle. Dynamic and leakage power depend on power supply and to reduce consumption of power, its supply has to be reduced which cannot be lowered beyond a certain limit as it impacts the speed of the circuit. There is trade-off between power and speed in digital circuit designs and so an optimum solution is always looked forward to. In the earlier period, the prime concern of varied large scale integration (VLSI) designer was area, performance, cost and reliability while power considerations were of only secondary significance. Motivated by, emerging battery operated devices like mobile phones, laptops, notebook etc. which demand more battery backup which can be achieved by decreasing the power consumption of the device that depends on standard cells used to implement device. The purpose of this paper is to suggest a technique which brings an optimum solution to the consumption of both static and dynamic power. Static and dynamic power can be reduced using high threshold voltage (vt) and sleep switch techniques respectively. The Technique proposed in this paper is a blend of both these techniques high vt and sleep switch. The proposed technique, Synergetic Power Consumption Technique will help to reduce both the power without affecting the speed of operation. The design will be implemented using high end Computer Aided Design (CAD) Tools. Standard test signals will be applied to design and power will be measured. Power consumption of digital circuit implemented with Synergetic Power Consumption Technique, Sleep-Switch technique and high-vt technique will be measured. For comparison, 8_bit ripple carry adder and dual rail domino 8_bit adder have been implemented with proposed technique and compared with the standard design. It has been observed that 23% of power is saved in case of 8_bit RCA with increase in delay by 20% and 37% of power is saved in case of dual rail domino with increase of 15% in delay.