Published Paper Details:

Quantum-dot cell automata (QCA) are an alluring rising innovation appropriate for the improvement of ultra-thick low-power elite advanced circuits. Effective arrangements have been proposed for a few number juggling circuits, for example, adders, multipliers, and comparators. By and by, since the plan of advanced circuits in QCA still represents a few difficulties, novel usage procedures and systems are very alluring. As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit, even though the design of logic modules in QCA is not always straightforward. In this brief, we propose a new adder that outperforms all state-of-the-art competitors and achieves the best area-delay trade off. The above advantages are obtained by using an overall area similar to the cheaper designs known in literature. The 16-bit, 32-bit and 64-bit version of the novel adder is implemented by verilog.