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  Published Paper Details:

  Paper Title

ANALYSIS AND REVIEW OF ALL RELAY PROCESSES AND DESIGN OPTIMIZATION FOR LOW VOLTAGE HIGH SPEED OPERATION

  Authors

  Soumitra S Pande,  Sanjeev Gupta

  Keywords

electrostatic force, digital integrated circuits, lithography, interconnects, parasitic effects, stiction

  Abstract


This paper focuses on relay process and design optimization. With optional additional lithography steps, we can achieve a more robust process required for eventual device scaling, highly reduced device footprint area, and the ability to form interconnects to fabricate circuits. Improved relay designs minimize parasitic electrostatic force issues and enhance functionality. The process flow is optimized to achieve the lowest switching voltages, while still ensuring reliable turn-off and avoiding stiction. New device concepts increase device functionality to reduce the number of structures required to achieve a certain function, and provide a new paradigm for designing circuits using relays.

  IJCRT's Publication Details

  Unique Identification Number - IJCRT1703003

  Paper ID - 170083

  Page Number(s) - 25-27

  Pubished in - Volume 5 | Issue 3 | September 2017

  DOI (Digital Object Identifier) -   

  Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882

  E-ISSN Number - 2320-2882

  Cite this article

  Soumitra S Pande,  Sanjeev Gupta,   "ANALYSIS AND REVIEW OF ALL RELAY PROCESSES AND DESIGN OPTIMIZATION FOR LOW VOLTAGE HIGH SPEED OPERATION", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.5, Issue 3, pp.25-27, September 2017, Available at :http://www.ijcrt.org/papers/IJCRT1703003.pdf

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ISSN: 2320-2882
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Journal Starting Year (ESTD) : 2013
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ISSN and 7.97 Impact Factor Details


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ISSN
ISSN: 2320-2882
Impact Factor: 7.97 and ISSN APPROVED
Journal Starting Year (ESTD) : 2013
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