ISSN2320-2882
Impact Factor9.17
UGC ParametersAligned
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CrossRefDOI
ESTD2013
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AccessOpen
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Paper Title
OPTIMIZING FPGA LOGIC BLOCK ARCHITECTURE FOR ARITHMETIC OPERATORS
Authors
J. Rangarajan , A. komala , C.Selvi , Anandakumar S
Keywords
Field programmable gate arrays, Digital arithmetic, Logic design, Design automation
Abstract
Hardened adder and carry logic is widely used in commercial FPGAs to improve the efficiency of arithmetic functions. There are many design choices and complexities associated with such hardening including: circuit design, FPGA architectural choices, and the CAD flow. However these choices have seen little study, and hence we explore a number of possibilities. We also highlight front-end elaboration optimizations that help ameliorate the restrictions placed on logic synthesis by hardened arithmetic. We show that hard adders and carry chains increase performance of simple adders by a factor of four or more, but on larger benchmark designs that contain arithmetic improve overall performance by 15% Approximate addition is a technique to trade off energy consumption and output quality in error-tolerant applications. a novel bit truncation approach is proposed to design dynamically energy-quality scalable adders with graceful degradation. As main idea, instead of being set to zero, the truncated input bits are set to the constant value that maximizes the output quality.
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IJCRT — journal style
"OPTIMIZING FPGA LOGIC BLOCK ARCHITECTURE FOR ARITHMETIC OPERATORS", IJCRT - International Journal of Creative Research Thoughts (www.ijcrt.org), ISSN:2320-2882, Vol.14, Issue 4, page no.e973-e981, April 2026, Available :https://ijcrt.org/papers/IJCRT2604582.pdf
APA — 7th edition
Rangarajan, J., komala, A., C.Selvi, & S, A. (2026). OPTIMIZING FPGA LOGIC BLOCK ARCHITECTURE FOR ARITHMETIC OPERATORS. International Journal of Creative Research Thoughts, 14(4), e973-e981. https://ijcrt.org/viewpaperforall.php?paper=IJCRT2604582
MLA — 9th edition
Rangarajan, J., et al. "OPTIMIZING FPGA LOGIC BLOCK ARCHITECTURE FOR ARITHMETIC OPERATORS." International Journal of Creative Research Thoughts, vol. 14, no. 4, 2026, pp. e973-e981, https://ijcrt.org/viewpaperforall.php?paper=IJCRT2604582.
Chicago — 17th, bibliography
Rangarajan, J., et al. "OPTIMIZING FPGA LOGIC BLOCK ARCHITECTURE FOR ARITHMETIC OPERATORS." International Journal of Creative Research Thoughts 14, no. 4 (2026): e973-e981. https://ijcrt.org/viewpaperforall.php?paper=IJCRT2604582.
Harvard — author–date
Rangarajan, J. et al. (2026) 'OPTIMIZING FPGA LOGIC BLOCK ARCHITECTURE FOR ARITHMETIC OPERATORS', International Journal of Creative Research Thoughts, 14(4), pp. e973-e981. Available at: https://ijcrt.org/viewpaperforall.php?paper=IJCRT2604582
IEEE — numbered reference
J. Rangarajan, A. komala, C.Selvi and A. S, "OPTIMIZING FPGA LOGIC BLOCK ARCHITECTURE FOR ARITHMETIC OPERATORS," IJCRT, vol. 14, no. 4, pp. e973-e981, Apr. 2026.
Vancouver — biomedical
Rangarajan J, komala A, C.Selvi, S A. OPTIMIZING FPGA LOGIC BLOCK ARCHITECTURE FOR ARITHMETIC OPERATORS. IJCRT. 2026 Apr;14(4):e973-e981.
AMA — 11th edition
Rangarajan J, komala A, C.Selvi, S A. OPTIMIZING FPGA LOGIC BLOCK ARCHITECTURE FOR ARITHMETIC OPERATORS. IJCRT. 2026;14(4):e973-e981. Accessed at https://ijcrt.org/viewpaperforall.php?paper=IJCRT2604582
BibTeX — Zotero, Mendeley, LaTeX
@article{IJCRT2604582,
author = {J. Rangarajan and A. komala and C.Selvi and Anandakumar S},
title = {OPTIMIZING FPGA LOGIC BLOCK ARCHITECTURE FOR ARITHMETIC OPERATORS},
journal = {International Journal of Creative Research Thoughts},
volume = {14},
number = {4},
pages = {e973-e981},
year = {2026},
month = {April},
issn = {2320-2882},
url = {https://ijcrt.org/viewpaperforall.php?paper=IJCRT2604582}
}
RIS — EndNote, RefWorks
TY - JOUR
AU - Rangarajan, J.
AU - komala, A.
AU - C.Selvi
AU - S, Anandakumar
TI - OPTIMIZING FPGA LOGIC BLOCK ARCHITECTURE FOR ARITHMETIC OPERATORS
T2 - International Journal of Creative Research Thoughts
JA - IJCRT
VL - 14
IS - 4
PY - 2026
SN - 2320-2882
UR - https://ijcrt.org/viewpaperforall.php?paper=IJCRT2604582
SP - e973-e981
ER -
Issue
Volume 14 Issue 4,
April-2026
Pages : e973-e981
Article Information
- Pages
- e973-e981
- Published
- April 2026
- Registration ID
- IJCRT_305996
- Published Paper ID
- IJCRT2604582
- Research Area
- Science and Technology
- Author Type
- Indian Author
- Location
- Rasipuram, Tamil Nadu, India
- Peer Review
- Request Peer Review Report
- Licence
- CC BY 4.0 · Open Access
- ISSN & Impact Factor
- 2320-2882 · IF 9.17
- Downloads
- 119
- Permanent Link
- https://ijcrt.org/viewpaperforall.php?paper=IJCRT2604582
- Published Paper PDF
- https://ijcrt.org/papers/IJCRT2604582.pdf
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