Published Paper Details:

The verification of integrated peripheral devices within System-on-Chip (SoC) designs remains a critical yet challenging task due to increasing complexity, heterogeneity, and the need for rapid development cycles. This review explores the landscape of software-based chip verification environments, focusing on modular, adaptive, and coverage-driven methodologies. By analyzing existing frameworks and proposing a hierarchical verification model, this paper highlights advances in adaptive stimulus generation and formal verification integration that significantly enhance verification efficiency and effectiveness. Experimental results demonstrate substantial improvements in verification time, bug detection rates, and coverage completeness. The review concludes by outlining future research avenues, emphasizing AI-driven test generation, cross-domain verification, and scalable architectures as vital to addressing evolving SoC challenges.