Published Paper Details:

Abstract: The Advanced Encryption Standard (AES) is a widely used symmetric key cryptographic algorithm ensuring secure data transmission. This paper presents an optimized AES implementation using Verilog HDL, enhancing both performance and resource efficiency. The design incorporates fundamental AES operations, including SubBytes, ShiftRows, MixColumns, and AddRoundKey, while employing optimization techniques to reduce latency and hardware utilization. A key enhancement is the reuse of the S-box for both encryption and decryption, with a multiplexer selecting between the two modes. Additionally, the MixColumns and AddRoundKey operations are integrated into a single unit to streamline processing. The proposed design further improves efficiency by reducing S-box instances through optimized key expansion, generating a 128-bit key every five cycles. Security is reinforced by extending the key size to 256 bits, with unique transformations applied across different encryption rounds. Functional simulation and synthesis results validate the correctness and effectiveness of the implementation, demonstrating its suitability for resource-constrained environments such as IoT devices and FPGA-based secure communication systems. This study highlights the advantages of Verilog HDL in cryptographic hardware design, offering scalability and flexibility for future advancements in encryption techniques.