Published Paper Details:

The Domino CMOS Logic Circuits are famously utilized in Very Large Scale Integrated (VLSI) structure. To design a VLSI circuit having low power and fast execution or high speed is the most testing task. By and by, one of the main goals is low power VLSI circuits with high speed. Full Adders are mainly used in various circuits which can perform various errands like development, duplication, division etc. In this manner it will diminish the force usage in full adders expects an enormous part of VLSI circuits having low power. In this paper, domino logic is used to manage a stable, particularly improved response for two constraints in full adder circuits i.e. power and delay. We review the Power, Delay and Power Delay Product (PDP) of 22T Domino Full Adder, 27T Domino Full Adder and 28T Static Full Adder. In this we also review these 3 circuit on the basis of different technology nodes or the feature length i.e. 45nm, 90nm and 180nm.